Conventional high quality and high performance video camera systems implement several image and video processor pipeline sections, each with several input streams and output streams. For low latency applications, an output stream from a pipeline section feeds to an input stream of another pipeline section through an on-chip stream buffer without going through an off-chip memory. The streams are synchronized though one-to-one semaphore counter operations. The pipeline that produces the output stream performs an increment-wait operation on a counter after storing a specified amount data in a stream buffer channel. The pipeline that consumes the output stream initially performs a receive-wait operation and a subsequent decrement operation on the counter after consuming the same amount of data.
It would be desirable to implement data unit synchronization between chained pipelines.